Multicore systems with core-level scratchpad memories offer appealing architectures for constructing efficient and predictable real-time systems. In this work, we aim to improve the usability of scratchpad memories and exploit their predictability to hide access latency to shared resources. We use a genetic algorithm to derive scheduling parameters for a set of directed acyclic taskgraphs (DAGs). DAGs consist of dependent subtasks and their respective communications, following the Acquisition Execution Restitution (AER) model. Subtasks are partitioned onto the multicore platform while scheduling their memory requests and relative communications onto the shared buses, in order to prevent interference and ensure predictability. Specifically, all subtasks and communications are assigned appropriate intermediate offsets and deadlines to guarantee that they comply with the system's timing constraints. We conducted a large set of synthetic experiments to demonstrate the effectiveness of the proposed technique.